Skills profile
– Analog and digital integrated circuit design through the Cadence ICFB IC design suite
– Physical layout verification of integrated circuits (LVS & DRC) using Allegro and Calibre
– Experienced in Linux and Linux scripting languages
– Xillinx ISE Design Suite
– Proficient in automation and use of standard laboratory test equipment
– Skilled in programming LabView, Vee, MatLab, VHDL, C/C++, Python

Work Experience
Foxconn Interconnect Technology                                      May 2016-Present

Test Engineer
– Redesigning the BBT test system in python to include: real time module state simulation, graphical station configuration, database storage of settings and test results
– Support current Vee based Black Box Test (BBT) system for CFP2, CXP and SFP fiber optic modules.
– Rework test station software and hardware to meet needs of new product research and development testing
– Design problem specific tests for firmware debugging
– Debug test station hardware and software

The Ohio State University, Physics Department                                      July 2002-2016
Research Assistant 2
ASIC design (2009 – 2016)
– Integral part of five ASIC designs and tap outs
– Physical layout and verification of four ASICs designed in IBM 0.13 um CMOS using Cadence Virtuoso, Alegro and Spectre, including design and verification of 12 channel 5 Gb/s vertical cavity surface emission laser (VCSEL) driver chip
– All ASICs tested and proven to function as simulated after fabrication
– Primary design engineer for a four channel 10 Gb/s VCSEL driver chip in TSMC 65 nm CMOS, currently in fabrication
– Integrate design blocks from collaborators in Europe
– Generate final GDS files and submit them to MOSIS fabrication
– Designed digital logic for ASICs using VHDL and Cadence RTL tools
– Install and maintain vendor supplied process design kits
Test System Design (July 2002-2016)
– Developed data acquisition systems and custom printed circuit boards for quality assurance testing of fiber optic transceiver modules and ASIC chips
– Designed automated quality assurance test systems for two production runs of fiber optic transceiver modules, including a 24 channel bit error rate tester using a Xilinx Spartan 6 FPGA and LabView software
– Designed hardware and LabView software for irradiation tests of fiber optic transceivers and ASICs at CERN
– Trained and managed undergraduate student workers, graduate students, and O.S.U. professional staff to ensure timely completion of optoelectronics assembly and testing

The Ohio State University, Columbus, Ohio                                     August 2012
Masters of Science in Electrical and Computer Engineering, GPA 3.272/4.0
The Ohio State University, Columbus, Ohio                                     December 2008
Bachelor of Science in Electrical and Computer Engineering
with Electrical Engineering Specialization, GPA 3.5/4.0
DeVry Institute of Technology, Columbus, Ohio                               June 2002
Bachelor of Science in Electronics Engineering Technology, GPA 4.0/4.0

Conference Papers
Gan, K. K.; Buchholz, P.; Kagan, H.P.; Kass, R. D.; Moore, J. R.; Smith, D. S.; Wiese, A.; Ziolkowski, M., “Radiation-hard ASICs for optical data transmission,” Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE , vol., no., pp.2109,2111, 23-29 Oct. 2011
Gan, K.K.; Buchholz, P.; Kagan, H.; Kass, R.D.; Moore, J.; Smith, D.S.; Wiese, A.; Ziolkowski, M., “Radiation-hard/high-speed parallel optical links,” Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE , vol., no., pp.674,677, Oct. 27 2012-Nov. 3 2012

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