4 Channel 10 Gbs VCSEL Driver

This past year (2014) I was responsible for designing and laying out a four channel 10 Gbs vertical cavity surface emission laser (VCSEL) driver integrated circuit (VDC) in Taiwan Semiconductor’s 65 nm CMOS process.  This was the fifth application specific integrated circuit (ASIC) I have worked on.  It is also the first of which I was the primary design engineer.  My responsibilities included everything from initial research, schematic capture, simulation through tape out.  Currently I am working on design and set up of the test system for the fabricated chip.

The chip itself was a “tiny” test chip (2mm square) and each of the four VDCs in the chip is slightly different, more on this later.  The basic design of all four channels is a CML or LVDS receiver directly DC coupled to the output driver. The output modulation and drive currents are adjustable via external voltages or internal DAC.

One design challenge was the threshold voltage of a VCEL is greater than 1V and TSMC 65nm CMOS is a 1.2V process.  This does not leave enough head room for modulating the output signal.  To solve this I negatively biased the VCSEL’s common cathode. This effectively lowers the threshold voltage of the VCEL as seen by the VDC and allows for a large modulation swing.

The four “flavours” of VDC are:

1. CML input with regular core MOSFETs
2. CML input, with some low threshold voltage MOSFETs for improved speed
3. CML input with regular MOSFETS and inductors in the power supply path of the final stage of the reviver and output driver for increased speed
4. same as 2 with a LVDS receiver input